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CYM9270 CYM9271B CYM9272A CYM9273
64K x 36 SRAM Module 128K x 36 SRAM Module 256K x 36 SRAM Module 512K x 36 SRAM Module
Features
* Operates at 50 MHz * Uses 64K x 18 / 128K x 18 or 256K x 18 high-performance synchronous SRAMs * 144-Position Angled DIMM from Berg p/n 61178 * 3.3V inputs/data outputs (9273) in plastic surface mount packages on an epoxy laminate board with pins. The modules are designed to be incorporated into large memory arrays. The modules are configured as single banks or multiple banks depending on the SRAM used to make the module. Separate clock are provided for each of the banks. Separate clocks are provided for each of the SRAMs. Multiple ground pins and on-board decoupling capacitors ensure high performance with maximum noise immunity. All components on the cache modules are surface mounted on a multi-layer epoxy laminate (FR-4) substrate. The contact pins are plated with 150 micro-inches of nickel covered by 30 micro-inches of gold flash.
Functional Description
The CYM9270, CYM9271B, CYM9272A, and the CYM9273 are high-performance synchronous memory modules organized as 64K(9270), 128K(9271B), 256K(9272A), 512K(9273) by 36 bits. These modules are constructed using either 128K x 18 SRAMs (9270, 9271B, 9272A) or 256K x 18 SRAMs
Logic Block Diagram - CYM9270
A[15:0] (2) 128K x 18 SRAMs A15:0 WE OE CS BW[0:3] ADSP CLK[0:1] OE CS SGW OE CS BWE WEH WEL ADSC CLK CLK[0:1] D[0:15] DQ[0:1] D[0:31] DQ[0:3]
Bank 0
PD1 64Kx36 GND
PD0 NC
Bank0
9270
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 May 19, 1999
CYM9270 CYM9271B CYM9272A CYM9273
Logic Block Diagram - CYM9271B/CYM9272A
A[16:0] (2) 128K x 18 SRAMs A16:0 WE OE[0:1] CS[0:1] BW[0:3] ADSP CLK[0:3] OE0 CS0 SGW OE CS BWE WEH WEL ADSC CLK D[0:15] DQ[0:1] D[0:31] DQ[0:3]
Bank0
CLK[0:1]
(2) 128K x 18 SRAMs A16:0 SGW OE1 CS1 OE CS BWE WEH WEL ADSC CLK D[0:15] DQ[0:1]
Bank1
PD 1 NC GND PD 0 GND GND
CLK[2:3]
9271B/72A
128Kx36 256KX36
Bank0 Bank0 and Bank1
2
CYM9270 CYM9271B CYM9272A CYM9273
Logic Block Diagram - CYM9273
A[17:0] (2) 256K x 18 SRAMs A17:0 WE OE[0:1] CS[0:1] BW[0:3] ADSP CLK[0:3] OE0 SGW OE D[0:15] DQ[0:1] D[0:31] DQ[0:3] CS[0] CS BWE WEH WEL ADSC CLK
Bank0
CLK[0:1]
(2) 256K x 18 SRAMs A17:0 SGW OE1 CS[1] OE CS BWE WEH WEL ADSC CLK D[0:15] DQ[0:1]
Bank1
PD1 512KX36 NC PD 0
CLK[2:3]
9273
NC
Bank0 and 1
3
CYM9270 CYM9271B CYM9272A CYM9273
PinConfiguration
Dual Read-Out SIMM (DIMM) Top View
GND A0 A2 A4 VCC3 NC NC GND A6 A8 A10 NC VCC3 A12 A14 A16 GND PD 0 GND BW[0] CS[0] GND CLK1 GND D0 VCC3 D2 D4 D6 GND VCC3 D8 D10 GND D12 D14 DQ0 NC NC GND WE NC VCC3 NC NC NC VCC3 NC NC NC GND BW[2] CS[1] VCC3 D 16 D18 NC NC NC GND CLK3 GND D 20 GND D 22 D 24 D 26 D 28 VCC3 D 30 DQ2 GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 GND A1 A3 A5 VCC3 NC NC GND A7 A9 A11 NC VCC3 A13 A15 A17 GND PD1 GND BW[1] OE[0] GND CLK0 GND D1 VCC3 D3 D5 D7 GND VCC3 D9 D11 GND D13 D15 DQ1 NC NC GND ADSP NC VCC3 NC NC NC V CC3 NC NC NC GND BW[3] OE[1] VCC3 D17 D19 NC NC NC GND CLK2 GND D21 GND D23 D25 D27 D 29 V CC3 D31 DQ3 GND
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CYM9270 CYM9271B CYM9272A CYM9273
Pin Definitions
Signal VCC3 GND A[17:0] ADSP OE[1:0] BW[0:3] WE CS[1:0] PD0-PD1 D[31:0] DQ[3:0] CLK[0:3] NC RSVD 3V Supply Ground Addresses from processor Address strobe from the processor Output Enables for each of the banks Byte writes Global Write Chip Select for the two banks Presence Detect output pins Data lines from processor Data Parity lines from processor Clock lines to the module. Signal not connected on module Reserved Description
Presence Detect Pins
PD1 CYM9270 - 64K x 36 CYM9271B - 128K x 36 CYM9272A - 256K x 36 CYM9273 - 512K x 36 GND NC GND NC PD0 NC GND GND NC
5
CYM9270 CYM9271B CYM9272A CYM9273
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied......................................... -0C to +70C 3.3V Supply Voltage to Ground Potential...... -0.5V to +4.5V DC Voltage Applied to Outputs in High Z State .............................................. -0.5V to +4.6V DC Input Voltage ........................................... -0.5V to +4.6V Output Current into Outputs (LOW)............................. 20 mA
Operating Range
Range Commercial AmbientTemperature 0C to +70C VCC 3.3V 5%
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VOH VOL ICC (9270) ICC (9271B) ICC (9272A) ICC (9273) Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage VCC Operating Supply Current VCC Operating Supply Current VCC Operating Supply Current VCC Operating Supply Current VCC=Min. IOH = -4 mA VCC=Min. IOL = 8 mA VCC=Max., IOUT=0 mA, f=fMAX=1/tRC VCC=Max., IOUT=0 mA, f=fMAX=1/tRC VCC=Max., IOUT=0 mA, f=fMAX=1/tRC VCC=Max., IOUT=0 mA, f=fMAX=1/tRC Test Condition Min. 2.2 -0.3 2.4 0.4 350 500 1000 1200 Max. VCC + 0.3 0.8 Unit V V V V mA mA mA mA
Capacitance[1]
Parameter CA Description Address Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9270 9271B 9272A 9273 9270 9271B 9272A 9273 9270 9271B 9272A 9273 9270 9271B 9272A 9273 Max. 12 7 14 20 12 8 16 20 9 5 10 16 6 3 3 5 Unit pF
CI
Control Input Capacitance
TA = 25C, f = 1 MHz, VCC = 5.0V
CO
Input / Output Capacitance
TA = 25C, f = 1 MHz, VCC = 5.0V
CCLK
Clock Capacitance
TA = 25C, f = 1 MHz, VCC = 5.0V
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
6
CYM9270 CYM9271B CYM9272A CYM9273
AC Test Loads and Waveforms[3]
R1 OUTPUT RL = 50 5 pF VL = 1.5V INCLUDING JIGAND SCOPE R2 GND 3 ns VCCQ OUTPUT ALL INPUT PULSES 3.3V 10% 90% 90% 10% 3 ns
(a)
(b)
[2]
Switching Characteristics Over the Operating Range
CYM9270 Parameter tCYC tCH tCL tAS tAH tCDV tDOH tWES tWEH tDS tDH tCSS tCSH tEOZ[4] tEOV Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise WH, WL Set-Up Before CLK Rise WH, WL Hold After CLK Rise Data Input Set-Up Before CLK Rise Data Input Hold After CLK Rise Chip Select Set-Up Chip Select Hold After CLK Rise OE HIGH to Output High Z OE LOW to Output Valid 7 3 3.1 0.5 3.3 0.5 3.1 0.5 7 7 3.1 0.5 7 7 Description Clock Cycle Time Min. 12 4 4 3 0.5 10.3 3 3.1 0.5 3.3 Max. CYM9271B Min. 12 4 4 3 0.5 10.3 3 3.1 0.5 3.3 0.5 3.1 0.5 7 7 Max. CYM9272A Min. 12 4 4 3 0.5 10.3 3 3.1 0.5 3.3 0.5 3.1 0.5 7 Max. CYM9273 Min. 12 4 4 3 0.5 10.3 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 2. Resistor values for VCCQ=3.3V are R1=317 and R2=351. 3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. All measurements are at room temperature. 4. tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
7
CYM9270 CYM9271B CYM9272A CYM9273
Switching Waveforms
Single Read[5]
tCH CLK tCSS CS tAS ADDRESS tADS ADSP tWES WH, WL
[6]
tCL
tCYC
tCSH
tAH
tADSH
tWEH
tCDV DATA OUT
tDOH
Single Write Timing
tCH CLK tCSS CS tAS ADDRESS tADS ADSP tWES WH, WL tDS DATA IN tDH tWEH tADSH tAH tCSH tCL
DATA OUT tEOZ OE
Notes: 5. OE is LOW throughout this operation. 6. ADSP has no effect on ADV, WL, and WH if CS is HIGH.
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CYM9270 CYM9271B CYM9272A CYM9273
Switching Waveforms (continued)
Output (Controlled by OE)
DATA OUT tEOZ OE tEOV
Output Timing (Controlled by CS)
CLK tADS ADSP tADS tADSH tCSS tCSS CS tCDV DATA OUT tCSOZ tCSH tCSH tADSH
Output Timing (Controlled by WH/ WL)
CLK tADS ADSP tWES WH, WL tWEOZ DATA OUT tWEOV tWEH tADSH tADS tADSH
Ordering Information
Speed( MHz) 50 Ordering Code CYM9270PM-50C CYM9271BPM-50C CYM9272APM-50C CYM9273PM-50C Document #: 38-M-00083-A Package Name PM45 PM45 PM46 PM46 Package Type 144-Pin Dual-Readout SIMM 144-Pin Dual-Readout SIMM 144-Pin Dual-Readout SIMM 144-Pin Dual-Readout SIMM Description Sync 64K x 36 Sync 128K x 36 Sync 256K x 36 Sync 512K x 36 Operating Range Commercial
9
CYM9270 CYM9271B CYM9272A CYM9273
Package Diagrams
144-Pin Single-Sided DIMM PM45
144-Pin Dual-Sided DIMM PM46
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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